{"id":"https://openalex.org/W1988807183","doi":"https://doi.org/10.1109/euc.2014.27","title":"A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared Memory","display_name":"A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared Memory","publication_year":2014,"publication_date":"2014-08-01","ids":{"openalex":"https://openalex.org/W1988807183","doi":"https://doi.org/10.1109/euc.2014.27","mag":"1988807183"},"language":"en","primary_location":{"id":"doi:10.1109/euc.2014.27","is_oa":false,"landing_page_url":"https://doi.org/10.1109/euc.2014.27","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 12th IEEE International Conference on Embedded and Ubiquitous Computing","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/11380/1171830","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029053093","display_name":"Paolo Burgio","orcid":"https://orcid.org/0000-0003-1954-7201"},"institutions":[{"id":"https://openalex.org/I2802204017","display_name":"Universit\u00e9 de Bretagne Sud","ror":"https://ror.org/04ed7fw48","country_code":"FR","type":"education","lineage":["https://openalex.org/I2802204017"]},{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["FR","IT"],"is_corresponding":false,"raw_author_name":"Paolo Burgio","raw_affiliation_strings":["DEI, Universit\u00e0 degli Studi di Bologna, Italy","LabSTICC, Universit\u00e9 de Bretagne-Sud, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEI, Universit\u00e0 degli Studi di Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"LabSTICC, Universit\u00e9 de Bretagne-Sud, France","institution_ids":["https://openalex.org/I2802204017"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061145921","display_name":"Andrea Marongiu","orcid":"https://orcid.org/0000-0003-1010-4762"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]},{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"Andrea Marongiu","raw_affiliation_strings":["DEI, Universit\u00e0 degli Studi di Bologna, Italy","Integrated Systems Laboratory, ETH, Zurich, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEI, Universit\u00e0 degli Studi di Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Integrated Systems Laboratory, ETH, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004215191","display_name":"Philippe Coussy","orcid":"https://orcid.org/0000-0002-7222-5271"},"institutions":[{"id":"https://openalex.org/I2802204017","display_name":"Universit\u00e9 de Bretagne Sud","ror":"https://ror.org/04ed7fw48","country_code":"FR","type":"education","lineage":["https://openalex.org/I2802204017"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Philippe Coussy","raw_affiliation_strings":["LabSTICC, Universit\u00e9 de Bretagne-Sud, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LabSTICC, Universit\u00e9 de Bretagne-Sud, France","institution_ids":["https://openalex.org/I2802204017"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]},{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["DEI, Universit\u00e0 degli Studi di Bologna, Italy","Integrated Systems Laboratory, ETH, Zurich, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEI, Universit\u00e0 degli Studi di Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Integrated Systems Laboratory, ETH, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6046,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.59187477,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"38","issue":null,"first_page":"130","last_page":"137"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8247503638267517},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5993692874908447},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5746649503707886},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.5404269695281982},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5147011876106262},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5113177299499512},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.47065606713294983},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.4356968104839325},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3380615711212158},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.26541537046432495},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.22091197967529297}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8247503638267517},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5993692874908447},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5746649503707886},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.5404269695281982},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5147011876106262},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5113177299499512},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.47065606713294983},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.4356968104839325},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3380615711212158},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.26541537046432495},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.22091197967529297},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/euc.2014.27","is_oa":false,"landing_page_url":"https://doi.org/10.1109/euc.2014.27","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 12th IEEE International Conference on Embedded and Ubiquitous Computing","raw_type":"proceedings-article"},{"id":"pmh:oai:cris.unibo.it:11585/525725","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/525725","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:iris.unimore.it:11380/1171830","is_oa":true,"landing_page_url":"http://hdl.handle.net/11380/1171830","pdf_url":null,"source":{"id":"https://openalex.org/S4306400718","display_name":"IRIS UNIMORE (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:iris.unimore.it:11380/1171830","is_oa":true,"landing_page_url":"http://hdl.handle.net/11380/1171830","pdf_url":null,"source":{"id":"https://openalex.org/S4306400718","display_name":"IRIS UNIMORE (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.75}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321877","display_name":"Fonds Unique Interminist\u00e9riel","ror":"https://ror.org/04nx63b17"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1492362130","https://openalex.org/W1971365469","https://openalex.org/W2024162789","https://openalex.org/W2051696543","https://openalex.org/W2054613700","https://openalex.org/W2062190012","https://openalex.org/W2072989594","https://openalex.org/W2075160498","https://openalex.org/W2098361319","https://openalex.org/W2099102876","https://openalex.org/W2126362242","https://openalex.org/W2132026091","https://openalex.org/W2133424003","https://openalex.org/W2135500365","https://openalex.org/W2147877714","https://openalex.org/W2153331583","https://openalex.org/W2163312341","https://openalex.org/W2164598857","https://openalex.org/W2167293499","https://openalex.org/W3144068561","https://openalex.org/W4233983581","https://openalex.org/W4245874061","https://openalex.org/W4249869867","https://openalex.org/W6629444575"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W2274562545","https://openalex.org/W2269990635","https://openalex.org/W3146054601","https://openalex.org/W2042762783","https://openalex.org/W4283730710","https://openalex.org/W4313484792","https://openalex.org/W2921149022","https://openalex.org/W4281784598","https://openalex.org/W4312985392"],"abstract_inverted_index":{"This":[0,123],"work":[1],"describes":[2],"how":[3],"we":[4,93],"use":[5,82],"High-Level":[6],"Synthesis":[7],"to":[8,32,38,172,198],"support":[9],"design":[10,96,134,193,202],"space":[11,97,203],"exploration":[12,98],"(DSE)":[13],"of":[14,35,51,83,99,136,142,146,156,185],"heterogeneous":[15,100],"many-core":[16],"systems.":[17],"Modern":[18],"embedded":[19],"systems":[20],"increasingly":[21],"couple":[22],"hardware":[23,66,113],"accelerators":[24,114,174],"and":[25,45,58,60,68,76,86,109,115,139,180],"processing":[26],"cores":[27,117],"on":[28,63,144],"the":[29,36,49,81,95,112,116,133,137,140,149,154,186,201],"same":[30],"chip,":[31],"trade":[33],"specialization":[34],"platform":[37,55,138],"an":[39,177],"application":[40],"domain":[41],"for":[42],"increased":[43],"performance":[44],"energy":[46],"efficiency.":[47],"However,":[48],"process":[50,135],"designing":[52],"such":[53,161],"a":[54,103,127,182,205],"is":[56,195],"complex":[57],"error-prone,":[59],"requires":[61],"skills":[62],"algorithmic":[64],"aspects,":[65],"synthesis,":[67],"software":[69],"engineering.":[70],"DSE":[71],"can":[72],"partially":[73],"be":[74],"automated,":[75],"thus":[77],"simplified,":[78],"by":[79],"coupling":[80],"HLS":[84],"tools":[85],"virtual":[87,207],"prototyping":[88],"platforms.":[89],"In":[90],"this":[91],"paper":[92],"enable":[94],"many-cores":[101],"adopting":[102],"shared-memory":[104,150],"architecture":[105],"template,":[106],"where":[107],"communication":[108,124],"synchronization":[110],"between":[111],"happens":[118],"through":[119],"L1":[120],"shared":[121],"memory.":[122],"infrastructure":[125],"leverages":[126],"\"zero-copy\"":[128],"scheme,":[129],"which":[130],"simplifies":[131],"both":[132],"development":[141],"applications":[143],"top":[145],"it.":[147],"Moreover,":[148],"template":[151],"perfectly":[152],"fits":[153],"semantics":[155],"several":[157],"high-level":[158],"programming":[159],"models,":[160],"as":[162],"OpenMP.":[163],"We":[164],"provide":[165],"programmers":[166],"with":[167],"simple":[168],"yet":[169],"powerful":[170],"abstractions":[171],"exploit":[173],"from":[175],"within":[176],"OpenMP":[178],"application,":[179],"propose":[181],"low-cost":[183],"implementation":[184],"necessary":[187],"runtime":[188],"support.":[189],"An":[190],"HLS-based":[191],"automatic":[192],"flow":[194],"set":[196],"up,":[197],"quickly":[199],"explore":[200],"using":[204],"cycle-accurate":[206],"platform.":[208]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2016-06-24T00:00:00"}
