{"id":"https://openalex.org/W1963813520","doi":"https://doi.org/10.1109/4.18610","title":"A systolic VSLI chip for implementing orthogonal transforms","display_name":"A systolic VSLI chip for implementing orthogonal transforms","publication_year":1989,"publication_date":"1989-04-01","ids":{"openalex":"https://openalex.org/W1963813520","doi":"https://doi.org/10.1109/4.18610","mag":"1963813520"},"language":"en","primary_location":{"id":"doi:10.1109/4.18610","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.18610","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033415719","display_name":"Wayne Burleson","orcid":"https://orcid.org/0000-0002-7068-4351"},"institutions":[{"id":"https://openalex.org/I188538660","display_name":"University of Colorado Boulder","ror":"https://ror.org/02ttsq026","country_code":"US","type":"education","lineage":["https://openalex.org/I188538660"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W.P. Burleson","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Colorado, Boulder, CO, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Colorado, Boulder, CO, USA","institution_ids":["https://openalex.org/I188538660"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080469112","display_name":"Louis L. Scharf","orcid":"https://orcid.org/0000-0003-1764-9335"},"institutions":[{"id":"https://openalex.org/I188538660","display_name":"University of Colorado Boulder","ror":"https://ror.org/02ttsq026","country_code":"US","type":"education","lineage":["https://openalex.org/I188538660"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L.L. Scharf","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Colorado, Boulder, CO, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Colorado, Boulder, CO, USA","institution_ids":["https://openalex.org/I188538660"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046214649","display_name":"Alexandre Gabriel","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A.R. Gabriel","raw_affiliation_strings":["Ball AeroSpace, Boulder, CO, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ball AeroSpace, Boulder, CO, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037266181","display_name":"Neil H. Endsley","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"N.H. Endsley","raw_affiliation_strings":["Ball AeroSpace, Boulder, CO, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ball AeroSpace, Boulder, CO, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9529,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.71970295,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"24","issue":"2","first_page":"466","last_page":"469"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10792","display_name":"Matrix Theory and Algorithms","score":0.9930999875068665,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7305700182914734},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.7300876975059509},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.6721133589744568},{"id":"https://openalex.org/keywords/discrete-cosine-transform","display_name":"Discrete cosine transform","score":0.6133615970611572},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6070038080215454},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4580788016319275},{"id":"https://openalex.org/keywords/trigonometry","display_name":"Trigonometry","score":0.45553210377693176},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.45246952772140503},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.44920647144317627},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4333624243736267},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3619775176048279},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3386108875274658},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.28836023807525635},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.23456159234046936},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20995160937309265},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1526329219341278},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.13985565304756165},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07570609450340271}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7305700182914734},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.7300876975059509},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.6721133589744568},{"id":"https://openalex.org/C2221639","wikidata":"https://www.wikidata.org/wiki/Q2877","display_name":"Discrete cosine transform","level":3,"score":0.6133615970611572},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6070038080215454},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4580788016319275},{"id":"https://openalex.org/C29001434","wikidata":"https://www.wikidata.org/wiki/Q8084","display_name":"Trigonometry","level":2,"score":0.45553210377693176},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.45246952772140503},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.44920647144317627},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4333624243736267},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3619775176048279},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3386108875274658},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.28836023807525635},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.23456159234046936},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20995160937309265},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1526329219341278},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.13985565304756165},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07570609450340271},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/4.18610","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.18610","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.41999998688697815,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1568994505","https://openalex.org/W1774267655","https://openalex.org/W2017369466","https://openalex.org/W2018649436","https://openalex.org/W2109536713","https://openalex.org/W2123008137","https://openalex.org/W2153691819"],"related_works":["https://openalex.org/W2165313046","https://openalex.org/W2128088646","https://openalex.org/W2094130026","https://openalex.org/W2143176207","https://openalex.org/W1988993989","https://openalex.org/W2127996712","https://openalex.org/W1988237207","https://openalex.org/W1941409175","https://openalex.org/W2160876944","https://openalex.org/W2382729611"],"abstract_inverted_index":{"The":[0,77,93],"design":[1],"of":[2,12,23,32,69,90,96,101,129],"a":[3,21,66,80,88,102,108],"systolic":[4,94],"VLSI":[5,60],"chip":[6,34,61,78,98],"is":[7,122],"described":[8],"for":[9,55],"the":[10,97,113,126,130],"implementing":[11],"signal":[13],"processing":[14],"algorithms":[15],"that":[16],"may":[17,47],"be":[18,48],"decomposed":[19],"into":[20],"product":[22],"simple":[24],"real":[25,85],"rotations.":[26],"These":[27],"include":[28,35],"orthogonal":[29],"transformations.":[30,44],"Applications":[31],"this":[33],"projections,":[36],"discrete":[37],"Fourier":[38],"and":[39,42,75,83,107,115],"cosine":[40],"transforms,":[41],"geometrical":[43],"Large":[45],"transforms":[46],"computed":[49],"by":[50],"'tilting'":[51],"together":[52],"many":[53],"chips":[54],"increased":[56],"throughput.":[57],"A":[58,118],"CMOS":[59],"containing":[62],"138000":[63],"transistors":[64],"in":[65],"5*3":[67],"array":[68],"rotators":[70],"has":[71,79],"been":[72],"designed,":[73],"fabricated,":[74],"tested.":[76],"32-MHz":[81],"clock":[82],"performs":[84],"rotations":[86],"at":[87,112],"rate":[89],"30":[91],"MHz.":[92],"nature":[95],"makes":[99],"use":[100],"fully":[103],"synchronous":[104],"bit-serial":[105],"interconnect":[106],"very":[109],"regular":[110],"structure":[111],"rotator":[114],"bit":[116],"levels.":[117],"distributed":[119],"arithmetic":[120],"scheme":[121],"used":[123],"to":[124],"implement":[125],"matrix-vector":[127],"multiplication":[128],"rotation.&gt;":[131]},"counts_by_year":[],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-10T00:00:00"}
