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Storage"],"published-print":{"date-parts":[[2024,8,31]]},"abstract":"<jats:p>Disaggregated memory (DM) is an increasingly prevalent architecture with high resource utilization. It separates computing and memory resources into two pools and interconnects them with fast networks. Existing range indexes on DM are based on B+ trees, which suffer from large inherent read and write amplifications. The read and write amplifications rapidly saturate the network bandwidth, resulting in low request throughput and high access latency of B+ trees on DM.<\/jats:p>\n          <jats:p>\n            In this article, we propose that the radix tree is more suitable for DM than the B+ tree due to smaller read and write amplifications. However, constructing a radix tree on DM is challenging due to the costly lock-based concurrency control, the bounded memory-side IOPS, and the complicated computing-side cache validation. To address these challenges, we design\n            <jats:bold>SMART<\/jats:bold>\n            , the first radix tree for disaggregated memory with high performance. Specifically, we leverage (1) a\n            <jats:italic>hybrid concurrency control<\/jats:italic>\n            scheme including lock-free internal nodes and fine-grained lock-based leaf nodes to reduce lock overhead, (2) a computing-side\n            <jats:italic>read-delegation and write-combining<\/jats:italic>\n            technique to break through the IOPS upper bound by reducing redundant I\/Os, and (3) a simple yet effective\n            <jats:italic>reverse check<\/jats:italic>\n            mechanism for computing-side cache validation. Experimental results show that SMART achieves 6.1\u00d7 higher throughput under typical write-intensive workloads and 2.8\u00d7 higher throughput under read-only workloads in YCSB benchmarks, compared with state-of-the-art B+ trees on DM.\n          <\/jats:p>","DOI":"10.1145\/3664289","type":"journal-article","created":{"date-parts":[[2024,5,8]],"date-time":"2024-05-08T11:28:05Z","timestamp":1715167685000},"page":"1-41","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A Memory-Disaggregated Radix Tree"],"prefix":"10.1145","volume":"20","author":[{"ORCID":"https:\/\/orcid.org\/0009-0005-0712-2195","authenticated-orcid":false,"given":"Xuchuan","family":"Luo","sequence":"first","affiliation":[{"name":"School of Computer Science, Fudan University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9982-5130","authenticated-orcid":false,"given":"Pengfei","family":"Zuo","sequence":"additional","affiliation":[{"name":"Huawei Cloud, Huawei Technologies Co Ltd, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-2855-2403","authenticated-orcid":false,"given":"Jiacheng","family":"Shen","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong, Hong Kong, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5831-9474","authenticated-orcid":false,"given":"Jiazhen","family":"Gu","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong, Hong Kong, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9405-4485","authenticated-orcid":false,"given":"Xin","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Computer Science, Fudan University, Shanghai, China and Shanghai Key Laboratory of Intelligent Information Processing, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3666-5798","authenticated-orcid":false,"given":"Michael","family":"Lyu","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong, Hong Kong, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9184-7383","authenticated-orcid":false,"given":"Yangfan","family":"Zhou","sequence":"additional","affiliation":[{"name":"School of Computer Science, Fudan University, Shanghai, China and Shanghai Key Laboratory of Intelligent Information Processing, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,6,6]]},"reference":[{"key":"e_1_3_4_2_2","doi-asserted-by":"publisher","DOI":"10.14778\/1453856.1453922"},{"key":"e_1_3_4_3_2","doi-asserted-by":"publisher","DOI":"10.1145\/3317550.3321433"},{"key":"e_1_3_4_4_2","doi-asserted-by":"publisher","DOI":"10.5555\/3485849.3485864"},{"key":"e_1_3_4_5_2","doi-asserted-by":"publisher","DOI":"10.1145\/2254756.2254766"},{"key":"e_1_3_4_6_2","doi-asserted-by":"publisher","DOI":"10.1145\/3387514.3405883"},{"key":"e_1_3_4_7_2","doi-asserted-by":"publisher","DOI":"10.1145\/3183713.3196896"},{"key":"e_1_3_4_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/3477132.3483587"},{"key":"e_1_3_4_9_2","doi-asserted-by":"publisher","DOI":"10.1145\/3448016.3457560"},{"key":"e_1_3_4_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/3152434.3152447"},{"key":"e_1_3_4_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/1807128.1807152"},{"key":"e_1_3_4_12_2","article-title":"Write Combining Memory Implementation Guidelines","author":"Corporation Intel","year":"1998","unstructured":"Intel Corporation. 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