{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:23:38Z","timestamp":1753885418237,"version":"3.29.0"},"reference-count":43,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,8,28]],"date-time":"2024-08-28T00:00:00Z","timestamp":1724803200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,8,28]],"date-time":"2024-08-28T00:00:00Z","timestamp":1724803200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,8,28]]},"DOI":"10.1109\/dsd64264.2024.00045","type":"proceedings-article","created":{"date-parts":[[2024,11,6]],"date-time":"2024-11-06T18:38:00Z","timestamp":1730918280000},"page":"282-290","source":"Crossref","is-referenced-by-count":1,"title":["Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+"],"prefix":"10.1109","author":[{"given":"Alejandro","family":"Serrano-Cases","sequence":"first","affiliation":[{"name":"Barcelona Supercomputing Center &#x0026; Unversity of Alicante,Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Enrico","family":"Mezzetti","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center,Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaume","family":"Abella","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center,Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francisco J.","family":"Cazorla","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center,Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2007.213"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289877"},{"journal-title":"Apollo 3.0 Software Architecture","article-title":"ApolloAuto","year":"2018","key":"ref3"},{"journal-title":"Perception","article-title":"ApolloAuto","year":"2018","key":"ref4"},{"journal-title":"ARM CoreLink QoS-400 Network Interconnect Advanced Quality of Service Supplement to ARM CoreLink NIC-400 Network Interconnect Technical Reference Manual","article-title":"Arm","year":"2017","key":"ref5"},{"journal-title":"ARM CoreLink QVN-400 Network Interconnect Advanced Quality of Service using Virtual Networks Supplement to ARM CoreLink NIC-400 Network Interconnect Technical Reference Manual","article-title":"Arm","year":"2017","key":"ref6"},{"journal-title":"Arm\u00ae Architecture Reference Manual Supplement Memory System Resource Partitioning and Monitoring (MPAM), for Armv8-A","article-title":"Arm","year":"2022","key":"ref7"},{"journal-title":"ARM CoreLink NIC-400 Network Interconnect Technical Refer-ence Manual","article-title":"Arm","year":"20XX","key":"ref8"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CSNET.2017.8241986"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS58335.2023.00023"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/12.919277"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247840"},{"journal-title":"General Acceptable Means of Compliance for Airwor-thiness of Products, Parts and Appliances (AMC-20). Amendment 23. Annex I to ED Decision 2022\/001\/R. AMC 20\u2013193 Use of multi-core processors. Technical report","article-title":"EASA, FAE","year":"2022","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DSN-W.2017.47"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2021.102298"},{"volume-title":"e6500 Core Reference Manual","year":"2014","key":"ref16"},{"key":"ref17","first-page":"1112016","article-title":"Freescale semicondutor. QorIQ T2080 Reference Manual","year":"2016","journal-title":"Also supports T2081. Doc. No.: T2080RM. Rev."},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-13-9193-4_9"},{"key":"ref19","first-page":"5:1","article-title":"Quasi isolation qos setups to control mpsoc contention in integrated software architectures","volume-title":"35th Euromicro Conference on Real- Time Systems, ECRTS 2023","author":"Garcia-Esteban"},{"article-title":"Performance isolation for real-time applications on multicore platforms using palloc and memguard","volume-title":"Proc. of Real-Time Linux Workshop (RTLWS)","author":"Gondi","key":"ref20"},{"issue":"2","key":"ref21","first-page":"32:1","article-title":"A survey on cache management mechanisms for real-time embedded systems","volume":"48","author":"Giovani","year":"2015","journal-title":"ACM Computing Surveys"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/CODES-ISSS.2013.6658988"},{"journal-title":"Intel\u00ae Resource Director Technology (Intel\u00ae RDT) on 2nd Generation Intel\u00ae Xeon\u00ae Scalable Processors Reference Manual, Rev. 1.0","article-title":"Intel","year":"2019","key":"ref23"},{"journal-title":"ISO\/DIS 26262. Road Vehicles - Functional Safety","article-title":"International Organization for Standardization","year":"2009","key":"ref24"},{"issue":"2","key":"ref25","first-page":"27:1","article-title":"A survey of techniques for cache partitioning in multicore processors","volume":"50","author":"Mittal","year":"2017","journal-title":"ACM Computing Surveys"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISIE.2010.5637677"},{"journal-title":"Processors and Microcontrollers","article-title":"NXP","year":"2024","key":"ref27"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2442116.2442129"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555764"},{"key":"ref30","first-page":"10:1","article-title":"Beyond the Weakly Hard Model: Measuring the Performance Cost of Deadline Misses","volume-title":"30th Euromicro Conference on Real-Time Systems (ECRTS 2018), volume 106 of Leibniz International Proceedings in Informatics (LIPIcs)","author":"Pazzaglia"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM48280.2020.00026"},{"key":"ref32","article-title":"Leveraging hardware qos to control contention in the xilinx zynq ultrascale+ mpsoc","author":"Alejandro","year":"2021","journal-title":"ECRTS"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS49844.2020.00039"},{"journal-title":"DesignWare Enhanced Universal DDR Memory Controller","article-title":"Synopsis","year":"20XX","key":"ref34"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISORC49007.2020.00030"},{"volume-title":"The basics of automotive radar","year":"2019","key":"ref36"},{"journal-title":"Arm-based processors","article-title":"TEXAS INSTRUMENTS","year":"2024","key":"ref37"},{"journal-title":"Rockwell Collins Uses Zynq UltraScale+ RFSoC Devices in Revolutionizing How Arrays are Produced and Fielded: Powered by Xilinx","article-title":"XILINX","year":"2018","key":"ref38"},{"key":"ref39","first-page":"UG1085","article-title":"XILINX","volume":"v2.l","year":"2019","journal-title":"Zynq UltraScale+ Device. Technical Reference Manual"},{"volume-title":"LogiCore AXI Traffic Generator","year":"2022","key":"ref40"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2013.6531079"},{"issue":"5","key":"ref42","first-page":"1095","article-title":"Profiling and controlling i\/o-related memory contention in cots heterogeneous platforms","volume":"52","author":"Zini","year":"2022","journal-title":"Software: Practice and Experience"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS58335.2023.00026"}],"event":{"name":"2024 27th Euromicro Conference on Digital System Design (DSD)","start":{"date-parts":[[2024,8,28]]},"location":"Paris, France","end":{"date-parts":[[2024,8,30]]}},"container-title":["2024 27th Euromicro Conference on Digital System Design (DSD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10741604\/10741607\/10741755.pdf?arnumber=10741755","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,11,27]],"date-time":"2024-11-27T13:39:08Z","timestamp":1732714748000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10741755\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,8,28]]},"references-count":43,"URL":"https:\/\/doi.org\/10.1109\/dsd64264.2024.00045","relation":{},"subject":[],"published":{"date-parts":[[2024,8,28]]}}}