The Ware for November 2025 is shown below.

This one is hopefully a bit easier to guess compared to last month’s ware! Pictured is just one board of a two board set, but the second board is a bit too much of a dead give-away so it’s been omitted. Thanks to Sam for thinking on her feet and snatching this board so that it could be donated to the contest!

Last month’s ware is an ADAS1010, described on the Analog devices website as a “15 Lead ECG Vital Signs Monitor Module with Respiration, Temperature and Blood Pressure Measurement”. It advertises a “robust, with electromagnetic interference (EMI), shock, and vibration resistant packaging”.

This is one of the more over-engineered solutions I’ve seen. I’m guessing that the middle layer of the three-layer stack is probably hollowed out, such that the surrounding boards create a Faraday cage. This would allow sensitive ECG front-end circuitry to be placed inside a shielded “container” that also doubles as a connector between the front and back boards.

This one was a real stumper, and it was interesting to see the discussion. I had redacted the DSP’s part number – ADSP-CM403 – because with that, an LLM could identify the board with a query such as “what boards have both an adsp-cm403 and an ice40 fpga”. That’s apparently a pretty unique part combination. When I saw it for the first time, I also couldn’t guess the ware; I kept on looking at the huge connector and assuming that some high-bandwidth, high-speed signals were involved. That’s an awful lot of pins for the advertised functions, but probably an insane amount of grounding/shielding is going on to isolate the sensitive ECG input lines.

I was betting the boards near-exclusive use of Analog Devices parts would be a tip-off that this was an Analog Devices module of some type, which would significantly narrow the space of possible functions. You kind of have to be on a very particular mission and/or have an unlimited budget to end up integrating that level of ADI parts on a board if you’re not actually ADI. To that end, megabytephreak got dangerously close to guessing it, so I’ll declare megabytephreak as the winner. Congrats, email me for your prize!

The Ware for October 2025 is shown below.

Thanks to Juan C. for contributing this curious ware!

I really can’t get enough of how the whole device is integrated with a multi-layer stacked PCB. I imagine that inside the middle of the stack there could be some interesting circuitry going on, too.

I redacted one part number to try and make things a smidge more challenging; at least, an LLM wasn’t able to outright guess the ware when that part number was omitted (but of course, the spirit of the game is to sharpen the wetware sitting on your shoulders by trying to reasoning about the function of the ware, with the aid of reference searches to find datasheets, learn theory, etc).

The Ware from September 2025 is a Hotronic AF 75 time base corrector. Really great comment thread, it was fun to read the sleuthing work and thought process behind the guesses. And yah, those SRAM chips make me nostalgic – I remember how expensive those were! Back when 32kiB cost real money.

A couple folks had guessed a time base corrector out of several possibilities, but I like how Guy Dunphy backed his guess up with an explanation of how it works. So, I’ll give Guy the prize this month. Congrats, drop me an email to collect your prize!

The Ware for September 2025 is shown below.

Thanks to Michael Dwyer for submitting this ware! I originally contemplated only showing the digital board to make the ware more challenging, but the analog part is so chaotically gorgeous I had to share it out of the aesthetic appreciation.

Despite the size and complexity of the system, there is no CPU. There was a day and age where it was fairly common to design systems without one. In many cases, a ROM-based FSM was more economical, offering better performance and consistent timing. This gave them an edge over MCUs when the flexibility afforded by a programmable instruction set was offset by higher component costs and the difficulty of working with variable-length, multi-cycle instruction execution timings.