I am trying to design a module in verilog that performs synthesizable modulo operation. I want to replace the % operator in the following algorithm with a synthesizable modulo opeation using generate block. Please help if you can. I have tried to create a block but its throwing errors during simulation in vivado.
Error :Module instantiation should be instance name.
Error2:Static evaluation of top level verilog unit in library work failed.
module modcalc(input [11:0]dividend,
input [11:0] divisor,
output reg [11:0] remainder);
reg [11:0] temp_dividend;
// Create a counter to count the number of iterations
reg [11:0] counter;
// Generate block to create the modulo operation
genvar i;
generate
for (i = 0; i < 11; i = i + 1) begin : MODULO_LOOP
always @(*) begin
if (temp_dividend >= divisor) begin
temp_dividend = temp_dividend - divisor;
end
end
end
endgenerate
// Assign the remainder to the output
always @(*) begin
remainder = temp_dividend;
end
endmodule
module montgomerymult(
input [3:0] A, B, // Operands
input [3:0] M, // Modulus
input [5:0] M_inv, // Precomputed value
input [4:0] r,
input [4:0] r_inv,
output reg[3:0] R , // Result
output [3:0] D
);
wire [9:0] H;
wire [11:0] T;
wire [11:0] Y;
reg [11:0] TL;
wire [11:0] m;
wire [3:0] K;
assign T = A * B;
//assign TL = (T) % (r); // Extract lower bits
modcalc(.dividend(T), .divisor(r), .remainder(TL));
assign m = (TL * M_inv) % (r); // Modular multiplication by M'
assign H = T + (m * M);
assign K =H /r;
always @* begin
if (K >= M)
begin
R <= K - M;
end
else begin
R <= K;
end
end
assign Y = T * r_inv;
assign D = Y % M;
endmodule
