how does this make syntax work?

Question

I am new to makefile. I have a makefile with following statement:

....

all: prepare hreader $(DIRS)
    echo $(DIRS)

.PHONY: prepare hreader $(DIRS)

prepare:                              
    mkdir -p ./lib
    $(MAKE) -C game_proc prepare     #here, why 'prepare'?!

hreader:
    make -C extra/hreader

$(DIRS):
    $(MAKE) -C $@

In my makefile directory, i have a 'game_proc' directory. And from GNU make tutorial, i know that below lines

prepare:                           
    mkdir -p ./lib
    $(MAKE) -C game_proc

will do a recursive make on 'game_proc'.

But why 'prepare' also appear in the recipe? Now how do i interpret '$(MAKE) -C game_proc prepare'? It does a recursive make on 'game_proc', and what? also a recursive make on 'prepare'?

Thanks,

tjltjl · Accepted Answer · 2012-12-09 14:29:19Z

1

A phony target just tells make that the rule is not going to create an output file of that name.

Update after comments

Ok, it's important to realize that there are two separate makefiles here at play:

./Makefile

and

game_proc/Makefile

The confusion results from there being a prepare target in both Makefiles.

I.e., there is in game_proc/Makefile a target prepare. Let's for a moment rename that target to prepare2 so that the situation becomes clearer:

./Makefile:

    .PHONY: prepare hreader $(DIRS)

prepare:                              
    mkdir -p ./lib
    $(MAKE) -C game_proc prepare2 # refers to game_proc/Makefile's prepare2 target

game_proc/Makefile:

prepare2:
    ...

edited Dec 9, 2012 at 14:29

answered Dec 8, 2012 at 9:55

tjltjl

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7 Comments

user1559625 Over a year ago

but this does not seem to answer my question, does it? could you elaborate more

tjltjl Over a year ago

Ah, I think I now understand what you mean. Are you concerned about what $(MAKE) -C game_proc prepare does when prepare has been declared phony? It has no effect there, because the phony declaration is valid for the current makefile only, not the Makefile in game_proc that the submake is going to be reading.

tripleee Over a year ago

So just to make the obvious explicit, a plain "make" runs the first target from the Makefile (in yours, that would be the all target, which is a common convention), and "make target" makes the target named "target" from the Makefile. If you have a recipe "tryme:" in your Makefile then make tryme will run those commands (and, by implication, create or update the file tryme in the current directory; although if it is declared a .PHONY: tryme then no file is involved).

user1559625 Over a year ago

@user1816548 omg, you're absolutely right, there IS a 'prepare' in game_proc/Makefile. So $(MAKE) -C game_proc prepare is only going to make 'prepare' in game_proc/Makefile?

user1559625 Over a year ago

@tripleee GNU tutorial only says '$(MAKE) -C dir' will do a recursive make for dir. i thought it means make the 1st target in dir/Makefile. But according to what you guys said, if the syntax is '$(MAKE) -C dir target', then it means make 'target' in dir/Makefile, right? Only like this can all make sense!

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