The configuration of the ADC is incorrect for two channels as the result only one ADC channel is running.

1. ADC_CR1_SCAN bit need to be enabled for more than 1 channel scan;

2. To have each ADC channel to be triggered by the interrupt, ADC_CR2_EOCS bit need to be enabled. Otherwise, only one interrupt would be generated at end of the sequence of all channel conversions.

3. Only one channel is configured to have sample rate of 84 cycles, you might want to setup the sample rate for the 2nd channel with

ADC1->SMPR2 |= ADC_SMP2_SMP0_2   // ch0 bit2 set = 84 sample cycle
            |  ADC_SMP2_SMP1_2;  // ch1 bit2 set = 84 sample cycles

Use pre-defined CMSIS definitions instead of magic number.

ADC1->CR2 |= ADC_CR2_SWSTART;

is more readable than

ADC1->CR2 |= (0x1 << 30);

The configuration of the ADC is incorrect for two channels as the result only one ADC channel is running.

1. ADC_CR1_SCAN bit need to be enabled for more than 1 channel scan;

2. To have each ADC channel to be triggered by the interrupt, ADC_CR2_EOCS bit need to be enabled. Otherwise, only one interrupt would be generated at end of the sequence of all channel conversions.

3. Only one channel is configured to have sample rate of 84 cycles, you might want to setup the sample rate for the 2nd channel with

ADC1->SMPR2 |= ADC_SMPR2_SMP0_2   // ch0 bit2 set = 84 sample cycle
            |  ADC_SMPR2_SMP1_2;  // ch1 bit2 set = 84 sample cycles

Use pre-defined CMSIS definitions instead of magic number.

ADC1->CR2 |= ADC_CR2_SWSTART;

is more readable than

ADC1->CR2 |= (0x1 << 30);