Are you sure initial doesn't work (you might have a typo in there...)?

initial begin
  for(int i=0; i<8; i++) begin
    test[i] = i;
  end
  $display(test[4]);
end

Are you sure initial doesn't work (you might have a typo in there...)?

initial begin
  for(int i=0; i<8; i++) begin
    test[i] = i;
  end
  $display(test[4]);
end

In systemverilog, something like the following will work. These are known as "Assignment Patterns":

integer test[7:0] = '{26, 40, 32, 18, 50, 0, 20, 12}; // note the '

I doubt either of the above are synthesisable, except maybe when targeting an FPGA.