From db67604b026933423d15a333c52c83e91086117b Mon Sep 17 00:00:00 2001 From: milesdig Date: Mon, 13 May 2019 14:36:28 +0100 Subject: [PATCH] Update README.md --- README.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 017ec22..16bc4ff 100644 --- a/README.md +++ b/README.md @@ -5,7 +5,7 @@ This is our design of a 16/32 bit microproccessor in VHDL, as part of the second year Computer Architectures module from the Department of Electronics at the University of York ## Authors -The Labs were created by myself [@zwrawr](https://github.com/zwrawr) and Tom meadows (Who dosent have a Git hub account :open_mouth: ). All of the commits are in my name because tom dosent have a github account, but the project is a join effort. +The Labs were created by myself [@zwrawr](https://github.com/zwrawr) and Tom meadows [@djw0bbl3](https://github.com/@djw0bbl3). All of the commits are in my name because tom didn't have a github account at the time, but the project is a join effort. ## Project The final assesment of the course was to create a 16/32 bit multi cycle cpu, using vhdl. @@ -19,6 +19,7 @@ This lab is about creating data paths for single cycle, multi cycle and piplined ![Image](/Lab_2/Report/DataPathD_Schem.png?raw=true) ## Homework -### Homework 1 +The homework assignments were manualy calcation caching hit or miss, hand assembling and lots of binary math. -### Homework 2 +## Project +Develop a multicycle proccessor. -- 2.11.4.GIT