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    @freakish Because addresses are in binary. Which means you can address aligned cache lines by dropping off the bottom n bits of the address bus when doing a memory access. And if cache lines are aligned to a power of 2 boundary, then everything else needs to align that boundary. Commented Nov 14, 2024 at 13:00
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    @freakish Whats important is that the cachelines/words are a power of two of the minimum addressable unit. Most modern machines have bytes as the minimum addressable unit, and so have power of two sized cachelines/words. Mainframes like the ICL 1900 were word addressable, and so they had 1 24 bit addressable unit per word. And 1 is a trivial power of 2. So if you are willing to have your base addressable unit be a multiple of 3 bits, it is doable, but that comes with a whole lot of bigger compromises when it comes to data interchangeability. Commented Nov 14, 2024 at 14:47
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    Its the bus geometry. For an m bit address you need m lines. For an m bit address aligned to the nth power of the base, you just take the top m-n lines, and that's the bus address. Any other scheme for calculating bus addresses is more complex and requires more lines. Commented Nov 14, 2024 at 16:39
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    @freakish Simplicitly is absolutely a goal of modern architectures. They are designed to be the simplest possible design that meets all the performance and compatibility requirements. Because complexity makes performance harder and reduces yields. If there is a solution that is simple, zero power, and zero latency? You better have a good reason for doing something else. Commented Nov 14, 2024 at 16:50
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    @freakish base 3 is annoyingly difficult to design for, because it just doesn't match how transistors work. You only get 2 saturation regions. Base 4 gets some interest, because you can work with a pair of transistors, but tends to only be seen in places where the density of signals massively outweighs the cost of processing hardware (storage, external highbandwidth interfaces etc). Commented Nov 14, 2024 at 23:27