Timeline for Low Latency Unix/Linux
Current License: CC BY-SA 3.0
9 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Sep 3, 2017 at 23:40 | comment | added | Sjoerd | @alexp You clearly don't know what you're talking about. FPGA is something different than "code burned into fast memory." | |
| Sep 3, 2017 at 20:35 | comment | added | alex p | For those who wants to know what is a hardware based solutions - it is mostly FPGA solutions where code is actually burned into the fast memory and is not changed withot reburning of so called ROM memory. Read Only | |
| Sep 3, 2017 at 20:21 | comment | added | Sjoerd | You describe the situation of 10 years ago. Hardware based solutions easily outperform pure C++ nowadays, no matter how optimized your C++ is. | |
| Sep 3, 2017 at 20:02 | comment | added | CodesInChaos | You might want to put some effort into spelling and formatting. In its current form, this post is barely comprehensible. | |
| Sep 3, 2017 at 20:01 | history | edited | CodesInChaos | CC BY-SA 3.0 |
added 12 characters in body
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| Sep 3, 2017 at 19:46 | review | Late answers | |||
| Sep 3, 2017 at 20:12 | |||||
| Sep 3, 2017 at 19:39 | history | edited | alex p | CC BY-SA 3.0 |
Some added details
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| Sep 3, 2017 at 19:31 | review | First posts | |||
| Sep 4, 2017 at 10:50 | |||||
| Sep 3, 2017 at 19:28 | history | answered | alex p | CC BY-SA 3.0 |