Timeline for Verilog UART Transmitter
Current License: CC BY-SA 4.0
8 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Oct 26, 2024 at 11:31 | answer | added | toolic | timeline score: 1 | |
| Oct 26, 2024 at 11:30 | history | edited | toolic | CC BY-SA 4.0 |
added 1 character in body
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| May 6, 2016 at 10:36 | history | edited | Mast♦ |
Removed superfluous tag.
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| Dec 28, 2015 at 23:41 | vote | accept | chasep255 | ||
| Dec 28, 2015 at 23:37 | answer | added | Greg | timeline score: 9 | |
| Dec 24, 2015 at 23:49 | history | edited | 200_success |
edited tags
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| Dec 24, 2015 at 20:46 | history | edited | Jamal | CC BY-SA 3.0 |
edited body
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| Dec 24, 2015 at 20:32 | history | asked | chasep255 | CC BY-SA 3.0 |